The hottest use of advanced EDA tools to meet the

2022-08-22
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How to reduce chip power consumption has become a hot issue in the semiconductor industry. In the past, for integrated device manufacturers (IDM), the most direct way is to use advanced process technology (stock code 002886) to publicly issue a shares for the first time. The listing ceremony was grandly held in Shenzhen Stock Exchange, and materials such as low-k media were used to solve the problem. Low power design can be achieved by combining the skills and experience of their own design team

however, after entering 90nm, the leakage current problem becomes increasingly prominent, and the CMOS static power consumption increases sharply, and power management begins to become an important consideration. This situation will be more serious below 65nm and 45nm, because the continuous reduction of process nodes leads to the thinner and thinner gate oxide layer, and the gate leakage increases exponentially. Finally, the dynamic power consumption is equal to the sub threshold leakage current, which is also equal to the gate leakage current. This forces the industry to adopt low-power design technology from the design end of IC

in order to meet these challenges, design engineers began to advocate the use of complex clock gate circuit switching schemes, thereby reducing unnecessary gate circuit switching operations. Nowadays, in order to meet the power goals, designers use various advanced low-power design techniques, including multi threshold design, multi voltage design, dynamic frequency and voltage scaling (dvfs), clock gating, memory with perceptible power consumption, power gating, and so on

carry out effective power evaluation in the early stage of design

there is no doubt that among the factors of product success, the time to market is one of the important factors, and sometimes even determines the success or failure of the product. Therefore, it is very important to solve the problem of potential low power consumption in the early stage of design to improve productivity

liang, senior consultant engineer of Synopsys, said that it is very important to evaluate the strategy and cost of low power consumption at the system level in the early design stage (i.e. system architecture stage) for the later implementation. The main aspects that should be paid attention to in the low-power strategy evaluated at this stage include: the division of system software and hardware, whether to adopt multi voltage, whether to adopt multi supply, whether to adopt on-chip or off chip power management, the selection of low-power IP, etc. At this stage of evaluation, on the one hand, through the evaluation experience of previous systems, on the other hand, through rapid prototype design, the power consumption of the design prototype can be estimated through eclypse system, so as to evaluate the effect of the common change price and power consumption saving of other relevant materials and technologies

Brad Miller, senior technical director of cadence, also expressed the same view. He said that the following five aspects will ensure designers to achieve their goals efficiently and accurately: 1 Determine the components that consume power in the design; 2. Adopt accurate switching behavior data; 3. Consider the simulation mode when generating switching behavior; 4. Adopt accurate line model; 5. Use a library that represents the worst-case power

f1: many designs are "connected" with respect to logic, but "disconnected" with respect to power consumption, and cannot automatically complete the design

a variety of low-power design solutions meet the power consumption challenge

however, EDA support for different low-power technologies is fragmented, resulting in designers having to define low-power functions through a series of special means. More importantly, the predictability and verification of the design become extremely difficult. At the same time, due to the complexity of the design and the previous lack of EDA automation means, the engineering design team is facing the problem of manually analyzing and applying these skills, and is not sure to meet the power consumption budget goal without affecting the performance

Relevant personnel of cadence company pointed out that many current designs can be said to be "connected" to logic, because all processes process logical information and can be completed automatically; This machine is equipped with a 10 fold explicit measurement microscope, but it is "disconnected" for power consumption, because for each process, power consumption issues are independent and affect each other. And the most important thing is that the power consumption design cannot be completed automatically, and many places need to be completed manually

therefore, effective low-power design requires collaboration between design teams, IP providers, and tool and solution providers. Only by implementing consistent methods and applying them to the whole tool field of the supply chain can the electronics industry truly solve the growing challenges faced by low-power design

f2: Synopsys eclypse low power solution

synopsys eclypse low power solution

eclypse solution supports standard unified power format (UPF) language and is compatible with low power design method guide (lpmm). A variety of low-power design technologies such as MTCMOS power gating, multi voltage, and dynamic voltage and frequency scaling (dvfs) have been adopted, which has greatly changed the engineers' chip design and verification. Designers can use enhanced clock gating and low-power clock tree synthesis to optimize the clock structure for low power consumption while taking into account clock jitter and timing goals; Multi threshold leakage current optimization uses options to limit the proportion of VT, providing optimal leakage current power optimization independent of design processing; The enhanced automation function of power switch insertion and optimization enables voltage drop and area limitation to be used for power consumption planning and hypothesis analysis

cadence low power design methodology kit

cadence's low power design methodology kit provides an end-to-end methodology covering logic design, functional verification and physical implementation. It uses SI2's general power consumption format (CPF) to provide a single low power intent specification in the whole process. The brocade bag includes a general wireless application design, which adopts methods such as multi supply voltage and power off technology, and includes relevant instruction scripts and technical documents that carry the design intent in the whole end-to-end process

this brocade bag is easy to combine and use, including six different processes: low-power function simulation, logic synthesis, design for testability (DFT) and automatic test vector generation (ATPG), physical design, formal implementation, verification and power grid signing. Users can implement the brocade bag as a complete process, or choose a separate selection module

f3: cadence low-power design methodology bag

ic1 generally needs to change the oil every 2000 to 4000 hours to design the low-power standard debate

since the beginning of 2007, around the standard for low-power IC design, the two EDA camps have launched fierce competition. One is CPF developed by cadence company and managed by SI2 (silicon integration initiative) low power alliance (LPC); The other is UPF supported by Synopsys, mentor graphics and magma design automation. Both UPF and CPF allow users to define power design intent and constraints in the entire RTL to GDSII design process, and their implementation methods are also very similar

Ju long, President of cadence Asia Pacific region, said that the advantage of CPF is user-centered - user driven and user adopted. The UPF standard is the response of CPF. Initially, CPF was not placed in the public domain because of some patent problems. But then cadence submitted it to IEEE, so that CPF can be open to the industry. He believes that from a design point of view, there is no need for two standards, because they actually discuss the same thing

bruce Jewett of Synopsys believes that UPF is an open language, and its advantage is favored by IEEE. As for whether the two standards will be integrated in the future, both EDA giants said that it all depends on the market and commercial interests. In fact, what users really care about is that they have certain solutions that can help them solve the current problems

according to the Nikkei BP news agency, Yoshio Inoue, chief engineer of the DFM and digital EDA Technology Department of Renesas, questioned the view of the two factions to build the whole low-power design process by concentrating EDA tools of various specifications. He said, "if a large number of common tools are used to build processes, it will be mixed with CPF and UPF tools. In this sense, the whole process of CPF and UPF is a piece of paper."

but another interesting situation is that archpro, which launched what Inoue calls a "super combination" of CPF and UPF and supports both static and dynamic verification specifications, was acquired by Synopsys in June 2007. In the eclypse low-power solution launched by Synopsys this time, we see the presence of archpro tools such as mvrc and mvsim. It can be predicted that in the future, the two camps are bound to launch a fierce battle around the low-power standard. (end)

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